module ALU(
    input logic [31:0] A,
    input logic [31:0] B,
    input logic [3:0] ALUctr,
    output logic [31:0] Result,
    output logic zero
    );
    
    logic SUBctr;
    logic SIGctr;
    logic [1:0] OPctr;
    ALUcontrol AC1(ALUctr,SUBctr,SIGctr,OPctr);
    
    logic [31:0] xor_result;
    XORarray X1(.a(B),
                .b({32{SUBctr}}),
                .xor_result(xor_result));
    logic [31:0] or_result;
    ORarray O1(.a(A),
                .b(B),
                .or_result(or_result));
    
    logic Add_carry;
    logic Add_Overflow;
    logic Add_Sign;
    logic [31:0] Add_Result;
    
    
    Adder Adder(
    .a(A),.b(xor_result),
    .Cin(SUBctr),
    .Add_carry(Add_carry),
    .zero(zero),
    .Add_Overflow(Add_Overflow),
    .Add_Sign(Add_Sign),
    .Add_Result(Add_Result) 
    );
    logic Less;
    _2for1MUX M2(
    .case0(Add_carry^SUBctr),
    .case1(Add_Overflow^Add_Sign),
    .SIGctr(SIGctr),
    .Less(Less)
    );
    _4for1MUX M4(
    .case0(Add_Result),
    .case1(or_result),
    .case2(B),
    .case3({31'b0,Less}),
    .OPctr(OPctr),
    .Result(Result)
    );
    
    
    
endmodule
